Semiconductor Scaling Shifts to Packaging, Photonics and System Integration

The semiconductor industry has reached the revenue milestone it once expected to hit years later. The next challenge is turning continued demand into systems that can be built reliably, at volume and at a cost customers can support. That puts the focus on more than transistor density: packaging, memory, power, cooling, photonics, inspection and test increasingly shape what a chip system can deliver.

At SEMICON West 2023 in San Francisco, the industry was forecasting $1 trillion in annual revenue by 2030. By SEMICON West 2026, it had already passed that mark. The show returned to San Francisco with a sold-out exhibit floor and more than 30,000 attendees, as companies faced a new question: how to keep pace with demand that has outrun earlier expectations.

SEMI President and CEO Ajit Manocha projected a market worth more than $2 trillion by 2030, with a possible $3 trillion by 2035. The association also projected $149 billion in spending on 300mm fab equipment this year, rising to $227 billion by 2029. Construction is due to begin on 20 new 300mm fabs or production lines in 2026 alone.

AI infrastructure is a major source of demand. Electrification, autonomous vehicles, robotics and industrial automation add to it. Yet the bigger shift is in the systems those chips must serve. More computing power brings new demands on memory bandwidth, power delivery and thermal control. The challenge is increasingly to make technologies work together as a product, rather than optimize each one in isolation.

“We’ve started talking about how to re-engineer engineering because you need to co-design and optimize across multiple intersections,” said Sassine Ghazi, president and CEO of Synopsys. That work, he said, spans physics, materials, process technology, architecture, design and software. The model itself helps define the workload, so engineers have to optimize across that stack.

Scaling now means coordinating the system

Several themes at the show led back to the same engineering problem. Advanced packaging is becoming part of system architecture. Photonics is moving closer to compute, bringing new assembly and test demands. Inspection and metrology must account for more complex structures and process histories. AI, meanwhile, is shifting from a workload the industry builds hardware for to a tool used in design and manufacturing.

These are not new technologies, but their interactions are becoming harder to manage separately. More compute increases pressure on memory bandwidth and power. Moving memory nearer to a processor can reduce data movement, but also concentrates heat. Splitting a large die into smaller components can improve yield and let each function use an appropriate process node. It also creates more connections that must be powered, cooled, assembled and tested.

Packaging is therefore taking on a larger role in determining system performance. “Packaging is no longer simply the place where semiconductor innovation ends,” said Lalitha Immaneni, vice president of semiconductor R&D at Intel Foundry. “Increasingly, it’s the place where system innovation begins.”

Memory, data movement, power delivery and thermal management now need to be considered as architectural choices. “The challenge is not to co-optimize one component,” Immaneni said. “It is to co-optimize across the system from end to end between silicon, packaging, and platform.”

Nitin Deshpande, Marvell’s vice president of advanced packaging, made a similar point at imec’s pre-show ITF USA program. “The package is really becoming a system where the compute, the memory, the interconnects, the power, the cooling, all of these things come together.”

Making those pieces function together is only the first step. Large packages that combine different kinds of dies must also reach production with acceptable yield, reliability and cost. “We can have very cool concepts, but if we cannot scale these into high volumes, if we cannot have a high-yielding, reliable process with a supply chain that can provide the parts in time, everything that we do cannot be converted into a business,” Deshpande said.

Patrick Vandenameele, CEO of imec, noted that companies can expand AI infrastructure by adding accelerators and racks. But adding more equipment is not the same as increasing semiconductor capability through traditional scaling. “These data centers are true engineering marvels,” he said. “But at the same time, this is not what we semiconductor people call scaling. It looks a little bit more like multiplication.”

The distinction is useful: transistor scaling remains important, but it no longer describes the whole task. Performance also depends on combining devices, materials and processes into a working system that can be manufactured repeatedly.

Fig. 2: Redefining a system. Source: SEMI

AI moves from assistance toward action

AI appeared across the show, but the discussion is moving beyond familiar uses such as design support, process control and defect classification. Generative AI has made it easier to interact with complex tools and data using natural language. Agentic systems add another step: an engineer can specify an outcome and let software call other tools, models or agents to pursue it.

“We started from an assistant copilot to generative capability to now what we’re describing as long-horizon autonomous agents, where instead of giving a prompt, you give an outcome,” Ghazi said.

The appeal is clearest in engineering tasks with too many variables for manual exploration. “The space that we’re optimizing in has exploded,” said David Fried, chief AI officer and corporate vice president of Semiverse Solutions at Lam Research. “We’ve now gotten to a place where the parameter set is intractable.”

Fried said a current Lam etcher can have a potential recipe space on the order of 10²³ possibilities. No engineer can evaluate that many combinations by hand. AI can search large, interconnected parameter and specification spaces, helping teams identify promising options and complex sensitivities.

Finding a pattern and acting on it are different jobs. A system that flags an unusual process signature is making a recommendation; one that changes a recipe or halts production is exercising control. That difference will matter as companies decide which decisions agents can make and what evidence they need first.

Ghazi said Synopsys has customer work in which autonomous agents can take a specification through verified RTL, a sequence that has traditionally required several engineers and months. People still define the architecture and approve the result before manufacturing. Even so, the example shows how the boundary between automated assistance and delegated work is moving.

For manufacturing teams, the open questions are practical. Which decisions need human approval? How much should an agent rely on physics-based models rather than statistical patterns? What validation is enough before an automated recommendation affects a production process? AI already has a role in semiconductor design and manufacturing. The new measure will be how much responsibility companies let it take on.

Fig. 3: What comes next is an evolving topic of great interest to a lot of people. Source: SEMI

Packaging needs evidence at every stage

Advanced packaging has moved past proving that heterogeneous integration can work. The pressing task is producing complex assemblies repeatedly and economically, while avoiding the loss of valuable components when a defect appears late. That changes what manufacturers need to know about each part before it enters the next stage.

Known-good die has long been a goal: attaching a faulty die can waste the package and the other components around it. As substrates, bridges and intermediate assemblies become more expensive, manufacturers are extending the same logic to those parts.

“Even though the bridge is a passive component with just metal lines, we sort it,” said Ravi Mahajan, Intel fellow and director of substrate and advanced packaging pathfinding at Intel Foundry. “We make sure we have known-good bridges going into a package, and what comes out should be a known-good package.”

Mahajan cautioned that “known-good” is a target, not a guarantee. A substrate can be inspected and tested, but no method can establish perfect certainty. Manufacturers add test features to improve coverage and reduce the uncertainty carried into assembly.

ASE follows a similar approach. In some fan-out flows, teams can test the interconnect structure before attaching active silicon. “The known-good methodology is what we’re striving for,” said Yin Chang, executive vice president of ASE. “Everything we do, every layer, we have the ability to confirm that it is good before we put on the most expensive part.”

Some silicon and HBM combinations can be worth as much as $30,000. ASE uses automated optical inspection and X-ray extensively, with AI helping to identify subtle differences in assemblies that may contain up to half a million joints. The aim is to reduce uncertainty before additional value is committed. As Chang put it, “It is too expensive already today. We just can’t scrap anything.”

Inspection cannot catch every issue at the earliest possible moment. Bonding creates interfaces that did not exist when individual components were examined. Heat, pressure and material interactions can also change an assembly, revealing defects only after another process step. Manufacturers therefore have to decide how much uncertainty they can accept before advancing a product, and where inspection will provide the most useful information.

Test and traceability extend across the build

As more functionality enters a package, test needs to cover properties that do not fit the usual digital pass-or-fail model. Optical devices can produce a range of acceptable responses, and engineers have to connect those measurements with likely defect causes. Co-packaged optics also changes the shape, density and handling requirements of the package.

“What our customers are demanding from OSATs is to be able to do dual-sided electrical/optical probe and expect efficiencies,” said Vineet Pancholi, senior director and manufacturing test technologist at Amkor. Customers still want efficient manufacturing tests, even when the assemblies have high selling prices.

The physical structure is changing too, Pancholi said, including package dimensions, weight and density. The broad sequence of probe, burn-in, final test and system-level test remains in place. Optical test is new to that sequence, however, and is expected to add time in the short term. Pancholi expects test times to fall as fabrication and assembly processes mature and defects become less common.

Finding the cause of a failure also depends on preserving information from earlier steps. Microtronic is retaining wafer images so teams can compare what a device looked like at different points in production. If a defect emerges later, those records can help narrow down where it began.

“Even if you don’t know exactly which level it is, you can bracket the issue from historical images,” said Reiner Fenske, CEO of Microtronic. He said customers value the retained history enough that throughput can become a secondary concern. The archive can preserve a lot’s images and data for retrieval months later.

Inspection results, wafer test, assembly records and earlier test insertions can all shape what happens next. Information can move forward to guide later checks, or backward to help identify process drift. Traceability becomes harder as a die moves from its original wafer coordinates through reconstructed wafers, panels and multi-die packages.

Test is becoming an evidence trail across manufacturing, rather than a single final gate. AI can help find patterns in that history, but the data must remain connected to the right device, process step and physical location. Without that context, more data alone won’t explain why a product failed.

Photonics brings alignment and yield into focus

Optical links can help address the power and signal-integrity limits of electrical connections as bandwidth and distance increase. That is pushing optics from pluggable modules nearer to compute, including near-package and co-packaged designs. As optics moves closer to the processor, its success depends more directly on semiconductor assembly methods.

“For precision bonding, it needs to not only control in all six degrees of freedom,” said Huan Ma, senior technologist at Intel Foundry. The process also needs semiconductor-scale throughput, automation and standardized material handling.

Materials must hold alignment through assembly, reflow and reliability stresses. Metrology must measure the features that predict optical performance. “We need to measure the geometry, the angles, the positions of optical features, and what really matters to the insertion loss and to the coupling efficiency,” Ma said. “Co-packaged optics will not scale just because the optics work. It will only scale when we industrialize the optics through advanced packaging.”

Companies described related manufacturing demands across the show floor. EV Group highlighted the time and measurement burden involved in checking multiple alignment points across hundreds of dies during die-to-wafer integration. Lam Research discussed waveguide fabrication, new modulator materials and fiber coupling. Advantest pointed to high-volume testing as a remaining constraint, with electro-optical probing and optical connectors adding steps that electrical test does not require.

Assembly can also change an optical path that met its specifications before integration. Alignment, bonding, thermal processing and fiber attachment all create opportunities for variation. “Coming through the door, you have an understanding of what is known good on the PIC and the EIC,” Mahajan said. “The biggest question is how do you ensure you have alignment? These processes in photonics are not recoverable and not reworkable, so we have spent a lot of time figuring out the yield limiters in assembly.”

Mahajan sees process learning as the path through these challenges. Fiber attachment, for example, was considered particularly difficult less than a decade ago, but improved through repeated manufacturing work. “I cannot think of any intrinsic showstoppers in any of these processes,” he said. “It’s now a matter of practice to do it right.”

The central question for co-packaged optics is shifting from whether it can function to how quickly manufacturers can align, inspect and test it at semiconductor volumes.

Engineering boundaries are becoming less useful

At SEMICON West, conversations about packaging often turned into conversations about heat. Memory placement raised questions about power. Photonics led to assembly and test. Inspection led to data management, then to AI. The organizational lines between engineering teams remain, but they increasingly fail to describe the physical system they are trying to build.

Immaneni described the next step as a move from design-technology co-optimization toward system-technology co-optimization: evaluating silicon, packaging and the platform together. A technology has to work in repeatable manufacturing to matter to customers. “A beautiful technology can be a good choice, but if I cannot manufacture it repeatedly, quickly, and with high quality, then it is not a customer technology,” she said.

Digital twins can help connect electrical, thermal, mechanical and manufacturing models, but only when the links between them are accurate enough to test the consequences of a change across domains. Ghazi also argued that teams need to include the workload in this picture: a model’s behavior can affect power use and thermal conditions in the hardware beneath it. When AI systems operate in robots and vehicles, sensors, real-time limits and reliability needs add more constraints.

Fig. 4: View from the show floor. Source: SEMI

SEMICON West is scheduled to move from San Francisco to the Phoenix Convention Center for its next event, March 30 through April 1, 2027, beginning a spring schedule. That leaves about five months between shows. By then, companies should have more to show on agent authority, inspection coverage, manufacturing data and the readiness of co-packaged optics for repeatable production.

Other markers include high-NA EUV moving toward production, power delivery shifting deeper into packages and materials suppliers being asked to account for interactions at interfaces and across process steps. Each development reinforces the same point: improving one component can expose the next constraint, so teams need to evaluate the whole path from design through assembly and test.

Three years ago, the industry was discussing how to reach $1 trillion by 2030. It has crossed that threshold early, and demand remains strong. The next gains will depend on building complex semiconductor systems quickly, reliably and economically. Transistor scaling is still part of the equation; the package, the data trail and the manufacturing process now help determine how far it takes the industry.

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